Transient Temperature Rise in Multi-chip Packages

All-copper Chip-to-substrate Interconnections for Flip-chip Packages

Singular stress fields at corners in flip-chip packages

An electronic device integrates diverse materials, and inevitably contains sharp features, such as interfaces and corners. When the device is subject to thermal and mechanical loads, the corners develop intense stress and are vulnerable sites to initiate failure. This paper analyzes stress fields at corners in flip-chip packages. The stress at a corner is a linear superposition of two modes of ...

Moisture absorption and desorption in wafer level chip scale packages

Article history: Received 28 May 2015 Received in revised form 18 June 2015 Accepted 29 June 2015 Available online xxxx

Endoscopic Inspection of Solder Joint Integrity in Chip Scale Packages

This paper reports, for the first time, the use of endoscopy for the nondestructive examination of solder joint integrity in chip scale packages (CSP) such as flip chip on flex (FCF). Borrowed from the medical instrument technology, the endoscope is used to examine visually the inside of an organ. This concept has now been developed and refined by ERSA and KURTZ, and led to an ERSASCOPE inspect...

Analysis of Solder Joint Reliability in Flip Chip Packages

Fatigue damage of solder joints is a serious reliability concern in electronic packaging. In this study, a flip chip package was modeled to investigate the effects of underfill material properties and BT substrate thickness on solder joint reliability. The CTE was found to have the main effect and matching CTE between underfill and solder joint is the most important consideration in the selecti...